How does signed (two's complement) addition handle overflow?

The bits are added exactly as for unsigned, but overflow shows up as an impossible sign change: pos + pos → negative, or neg + neg → positive.

Positive overflow: Two positive numbers sum to negative Negative overflow: Two negative numbers sum to positive

Example (4-bit, range -8 to +7):

5 + 4 = 9, but wraps to -7 (positive overflow)
  0101 (+5)
+ 0100 (+4)