Quiz Entry - updated: 2026.07.14
What are the three packet forwarding mechanisms on Cisco routers, and which is the modern default?
The three mechanisms are: Process Switching (old, CPU per-packet), Fast Switching (cached, CPU for first packet only), and Cisco Express Forwarding (CEF — modern default, hardware-based, all packets forwarded without CPU).
* Evolution of Cisco forwarding mechanisms. *
* CEF (Cisco Express Forwarding) internals: FIB (Forwarding Information Base) plus adjacency table. *
| Mechanism | How It Works | Performance | When Used |
|---|---|---|---|
| Process Switching | Every packet sent to CPU for routing table lookup | Slowest — CPU bottleneck | Legacy, or for packets requiring special handling |
| Fast Switching | First packet to a destination is process-switched; result is cached. Subsequent packets to same destination use the cache | Faster — cache hit avoids CPU | Legacy (predecessor to CEF) |
| CEF (Cisco Express Forwarding) | Pre-builds a FIB (Forwarding Information Base) and adjacency table from the routing table. All packets forwarded in hardware | Fastest — line-rate forwarding | Modern default on all Cisco routers and L3 switches |
CEF in detail:
- FIB (Forwarding Information Base): Pre-computed from the routing table — contains the forwarding decision for every known destination. Updated only when the topology changes (not per-packet)
- Adjacency table: Pre-resolved Layer 2 next-hop information (from ARP (Address Resolution Protocol)). Contains the MAC (Media Access Control) addresses needed for re-encapsulation
Why CEF is so fast:
- No CPU involvement per-packet — forwarding is done in hardware (ASICs)
- FIB and adjacency tables are change-triggered, not packet-triggered
- All packets are forwarded at line rate regardless of routing table size
Tip: CEF is enabled by default. The only time you'd see process switching is for certain control plane packets (e.g., packets destined for the router itself, or when debugging).
Go deeper:
Cisco Express Forwarding (Wikipedia) — the modern default mechanism and its FIB + adjacency-table internals.