What is the Time Stamp Counter (TSC) and how is it used?

The Time Stamp Counter is a 64-bit register that increments every clock cycle; read it with the rdtsc instruction for cycle-accurate timing.

TSC properties:

• Special register in Intel-compatible CPUs
• Incremented every clock cycle
• Read with rdtsc instruction

Reading TSC in C (inline assembly):

void read_tsc(unsigned int *hi, unsigned int *lo)
{
    asm volatile("rdtsc; movl %%edx, %0; movl %%eax, %1"
        : "=r" (*hi), "=r" (*lo)
        :
        : "%edx", "%eax");
}

Usage - measuring function execution:

// Start time
read_tsc(&s_hi, &s_lo);
// Function to measure
fib(n);
// End time
read_tsc(&e_hi, &e_lo);

// Cycles elapsed
diff = (e_hi:e_lo) - (s_hi:s_lo);

This gives cycle-accurate measurements for performance analysis.

Go deeper:

• Time Stamp Counter (Wikipedia) — the 64-bit x86 cycle counter, RDTSC, its multicore/frequency pitfalls, and use in timing side-channels.
• x86 instruction listings: RDTSC (Wikipedia) — RDTSC (opcode 0F 31) reads the TSC into EDX:EAX.