Fetch → decode → execute, repeated endlessly as long as there is power — the processor reads the next instruction, works out what it means, and carries it out.

* A processor endlessly repeats fetch, decode and execute for each instruction, as long as it has power. *

At its heart a CPU is a simple loop. It maintains a program counter (the address of the next instruction), and on each turn it:

1. Fetches the next instruction — which raises the questions "what is the next instruction?" and "fetch it from where?"
2. Decodes it — works out the instruction format, which operation it is, what operands it takes, and where those operands come from and go to.
3. Executes it — actually performs the operation, then advances the program counter and loops.

Everything else in this topic hangs off this cycle. The ISA is the agreement that answers the decode questions (what instructions exist, what operands mean); the registers and memory are where operands live; the condition codes record results of execution; and control instructions (jumps, calls) change which instruction gets fetched next. Keeping this fetch-decode-execute loop in mind turns a pile of assembly facts into one coherent picture.

Go deeper:

• Instruction cycle (Wikipedia) — the fetch-decode-execute loop with a state diagram of each step.