What does RISC stand for and what characterizes it?

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RISC = Reduced Instruction Set Computer: a small set of simple, fixed-length instructions where only explicit load/store instructions touch memory.
RISC bets that simple, uniform instructions are easier to make fast. Each instruction is the same width (commonly 32 bits), so the CPU can decode and pipeline them mechanically. Crucially it is a load/store architecture: arithmetic works only on registers, and separate load/store instructions are the only way to move data to and from memory. To compensate for not operating on memory directly, RISC chips provide many registers.
The same memory-multiply-add that one CISC instruction did becomes a short, explicit sequence:
ldr r0, [r1, r2, lsl #2]   # load from memory[r1 + r2*4]
add r3, r3, r0             # add it into a register

Advantage: simple decoder, easy pipelining, predictable timing.
Disadvantage: more instructions and larger code size.
Examples: ARM, RISC-V, MIPS, SPARC, PowerPC.
Go deeper:

RISC (Wikipedia) — the load/store model and simple fixed-length instructions.